Multipath sonar simulator

ABSTRACT

Part of the output of an active signal generator is delayed, phase shifted and recombined with the remainder of the output to form an input to an echo generator. Part of the output of a passive signal generator is likewise delayed, phase shifted and recombined with the passive signal generator output prior to being combined with the output of the echo synthesizer to provide signals simulative of multipath sonar characteristics. A controllable delay network utilizing shift register means is disclosed.

United States Patent [1 1 Murphree Jan. 29, 1974 MULTIPATH SONARSIMULATOR (75] Inventor: Francis J. Murphree, Winter Park,

Fla.

[73] Assignee: The United States of America as represented by theSecretary of the Navy, Washington, DC.

[22] Filed: Feb. 22, 1971 [2ll Appl. No.: 117,585

3,363,045 l/l968 Pommerening 35/l0.4

Primary ExaminerMaynard R. Wilbur Assistant Examiner-43. E. MontoneAttorney, Agent, or FirmR. S. Sciascia; J. W. Pease;

H. A. David [57] ABSTRACT Part of the output of an active signalgenerator is delayed, phase shifted and recombined with the remainder ofthe output to form an input to an echo genera- [52] US. Cl. 35/ 10.4I01. Part Of the output of a passive signal generator is [51] Int. Cl.G09!) 9/00 likewise el ye p e s e and recombined with [58] Field ofSearch 35/ 10.4; 340/5 D he passive Signal generator output prior tobeing combined with the output of the echo synthesizer to pro- [56]Refer e Cit d vide signals simulative of multipath sonar characteris-UNITED STATES PATENTS tics. A controllable delay network utilizing shiftregis- 3,555,165 1 1971 Ettenhofer 35/l0.4 ter means dlsclosed'3,484,738 l2/l969 Autrey 35/l0.4 7 Claims, 2 Drawing Figures 10 ls 22 32,3e

as ACTQIENSAOSFAR CONTgEOE-LkYABLE V VARIABLE PHASE GENERATOR SI NETWORKATTENUATOR SHlFTER SUMMING NETWORK ze 42 ,42 PROBLEM com uree Z Si NALVARIABLES GENERATOR ECHO 5s SYNTHESlZER 46 s3 58 52 l6 1 5 5? s4VARIABLE 7 fi f SUMMING ATTENUATOR NETWORK NETWORK 6H2 {*"60 54 I500 64PHASE 5 SUMMING SHlFTER NETWORK GG -l TO UT/LIZATlON MEANS MULTIPATHSONAR SIMULATOR STATEMENT OF GOVERNMENT INTEREST The invention describedherein may be manufactured and used by or for the Government of theUnited States of America for governmental purposes without the paymentof any royalties thereon or therefor.

BACKGROUND OF THE INVENTION This invention relates to sonar simulationand more particularly to apparatus for generating signals simulative ofactive or passive sound signals arriving at a receiver via a pluralityof paths from a target.

One major effect of multi-path transmission is to cause fluctuations inthe amplitude of each frequency component of a multi-frequency signal asthe separation between source and receiver changes, because of thechanging phase relation between direct and delayed components of eachsignal. The phase shift between two signals arriving at a given pointwith a difference of transmission time A! is 21rfAt, where f is thefrequency of the sonar signal. If 21rfAl is an odd multiple of 11' (andno phase shift occurs at the reflecting surface) the sum of the delayedand direct signals is a minimum. The opposite is true if 21rfAt O or isan even multiple of 11'. Signals of differing frequency will usually beof unequal amplitude at the receiving point, even though their sourceamplitudes may have been the same, because 21rfAt depends on frequency.This complicates the simulation problem if the source contains manycomponents. In the case of active sonar, multipath stretches the echoand may obscure information that would otherwise be apparent.

The magntiude of At depends upon the geometry of the multipathsituation. A typical case exists where a signal originating at a sourcetravels to a receiver via a direct path and also via a surface reflectedpath. In this case At 2 d d /r v, (t)

where d is the depth of the source, d the depth of the receiver, r isthe horizontal separation (range) between source and receiver and v isthe velocity of sound in water. (This relation is derived in UnderwaterAcoustic Handbook by Vernon M. Albers, Vol. II, page 50).

If the siganl originating at the source is reflected back by the target,then the delay between the echo that travels forth and back by thedirect path and the echo which travels in both directions by the surfacereflected path is 2Ar. Two additional pairs of paths are possible,namely that which is direct going from source to target and is reflectedgoing from target to receiver, and that which is reflected during travelfrom source to target and is direct going from target to receiver. Notall paths will necessarily be effective in any given case, The relativedelay of the longer path compared to the direct path is A! for bothcases. As stated above, the phase difference between a direct path and amultipath signal (or any pair of paths of different length) signal dueto a delay A! is 21rfAt. The total phase difference must include thephase shift occuring at reflection.

In past or proposed devices the effects of multipath:

have been roughly approximated by introducing random fluctuations intothe amplitude of the simulated signal. In laboratory experiments theefi'ect of multipath has been approximated by the use of fixed delaylines. In the training-simulation field the problem has not receivedwidespread attention probably because of the extensive use of magneticrecordings for training purposes. Recordings made of actual signals ofcource contain all of the effects one has to otherwise simulate.

Unfortunately the use of taped actual signals limits the simultion tothe circumstances of the recording and does not permit changes in theprogram as may be desired for simulation of varying tactical situationsand the like. Moreover, the large bandwidth which is required to berecorded to render simulation of the barrel stave type sonar system hasrequired use of very high speed recorder/reproducers which haveexperienced in inordinately high breakdown rate.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic illustration,in block form, of a multipath sonar simulator embodying the inven tion;and

FIG. 2 is a diagrammatic illustration, in block form and in greaterdetail, of a controllable delay network forming part of the simulator ofFIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the form of the inventionillustrated in FIG. 1 and described hereinafter, a multipath simulator10 comprises a passive signal generator 12 the output of which,represented by flow line 14, may include signals simulative of thosewhich might emanate from a target, eg. propellor beat, machinery noise,etc. Such generators are well known by those skilled in the art to whichthe invention pertains and need not be described in detail, The passivesignal output 14 is connected as one input to a summing network 16.

A second input to the summing network 16 is derived from an active sonarsignal generator 18 which may conveniently generate a signal simulativeof CW sonar ping, FM. slide, or whatever character sonar is desired. Theactive sonar signal generator may in some cases be an operational sonarapparatus but may also be apparatus such as those well known in thesimulation art for generating electrical signals simulative of activesonar active pings. The output of the active sonar generator 18 isapplied as shown by line 20 to a controllable delay network 22, and byline 20a to a summing network 24.

The controllable delay hetwork 22, which will later be described in moredetail with reference to FIG. 2, is responsive to a delay command signalreceived from a computer 26 via line 28, to provide a delayed activesonar signal on line 30 to a variable attenuator 32.

The delay introduced by the network 22 represents the time for a sonarsignal to travel from a sonar source to a target by a reflective path.for example by surface reflection or by reflection off of a thermalboundary. The computer 26 provides appropriate delay commands on line 28in accordance with problem variables such as the depth of the sonarsource, the depth of the target, and target range. all of which problemvariables are represented collectively by line 34.

The delayed active sonar signal is suitably attenuated by attenuator 32and passed as shown by line 36 to a phase shifter 38. The phase shifter38 introduces a change of phase corresponding to that which occurs inoperational sonar signals upon reflection from a surface, and passes thephase shifted signal as shown by line 40 to the summing network 24.

The summing network 24 combines the direct path active sonar signalreceived via line a with the reflected path active signal received vialine to provide a composite active sonar signal, represented by line 42,to an echo synthesizer 44. This composite signal on line 42 may beconsidered to be the total target illuminating signal.

The echo synthesizer 44, which is desirably of the character describedin copending patent application Ser. No. 94,134, filed Dec. l, l970,provides electrical signals on line 46 simulative of aspect dependent,highlighted sonar echoes. These active sonar signal echoes are appliedvia line 46 as a second input to the summing network 16 where they arecombined with passive sonar signals from the passive signal generator 12to provide on line 50 a composite of all signals leaving the targetwhether active or passive. The composite signals are applied via line 50to a controllable delay network 52 and via line 50a to a summing network54.

The controllable delay network 52 may be a duplicate of the network 22and introduces, in response to delay commands via line 56 from thecomputer 26, a delay which represents the amount by which the timerequired for signals to arrive at the sonar receiver by a reflectivepath exceeds the time required for signals to arrive from the target bya direct path. The dealyed composite echo and passive signals areapplied as shown by line 57 to a variable attenuator 58 which attenuatesthe signals and passes them by line 60 to a phase shifter 62. The phaseshifter 62 introduces a phase change simulative of that which occurs inan actual reflective path and passes the phase changed signal via line64 as one input to the summing network 54. The other input to thesumming network 54 is the output of the summing network 16 via lines 50,50a and represents signals traveling to the sonar receiver from thetarget along a direct path.

The summing network 54 combines the reflected path signals from phaseshifter 62 with the direct path signals from the summing network 16 toprovide an output on line 66 which is fully simulative of sonarreception involving both active and passive signals and involving bothdirect and indirect transmission paths to and from the target.

At times it may be desirable in rendering realistic training toeliminate one or the other, or both, of the reflective paths, or toeliminate either active or passive signals. To this end, switches S1,S2, S3, and S4 are in cluded in lines 14, 20, 40, and 50, respectively.These switches may be used in various combinations to provide thedesired degree of simulation.

Referring now to FIG. 2, there is illustrated in more detail thepreferred form of controllable delay network 22 which achieves avariable time delay through the agency of what may be termed a shiftregister delay line. The network 22 comprises a low pass input filter 70connected to pass its output as shown by line 72 to the input of an nbit analog to digital converter 74 having parallel output lines 74 79, nbeing taken as five for purposes of illustration. This converter 74serves, when actuated by a suitable read signal, to read out digitallythe amplitude of the input thereto from filter 70. The output lines 75-79 are connected as inputs to AND gates 80 84, respectively, the outputlines 89 of which are connected as the inputs to an n channelparallel-in/parallel-out shift register 90.

The shift register 90 has its parallel output lines 91 95 connected asinputs to AND gates 96 100, respectively, the output lines 101 105 ofwhich are connected as inputs to a digital to analog converter 108. Theconverter 108 has its output connected as shown by line 110 to a lowpass output filter 112, the output of which is on line 30.

Provision is made, according to the usual practice with shift registersand digital to analog converters, to initially clear the converter 74and the register 90. This is represented by lines 114 and 116,respectively.

Actuating of the converter 74, enabling of the AND gates 80 84, shiftingof the register 90, and enabling of the AND gates 96 100 are effected bytiming means which derive the necessary gating and shift signals fromthe output of the computer 26 on line 28, which output has beendescribed as the reciprocal of the time differential between the directand the reflected paths, i.e. l/At. The timing means comprises a digitalto analog converter which receives the input via line 28. The output ofconverter 120 is an analog voltage represented by line 122 connected asthe controlling input to a voltage to frequency converter 124 which maybe in the form of a voltage controlled oscillator.

The sine wave output of converter 124 on line 125 is shaped to series ofpulses of predetermined width by a singleshot multivibrator 126 andapplied as shown by line 127 to a divide by n divider 128. The output ofthe divider 128 on line 130 is shaped to a series of pulses ofpredetermined width by a singleshot multivibrator 132 and passed vialine 134, a fixed delay means 136 and lines 138 and 140 144 to AND gate80 84, and also to an n pulse generator 146. The output of the divider128 and singleshot multivibrator 132 is also applied via line 148 as theread signal to the converter 74, and via line 150 as the enablingsignals for the AND gates 96 100, all as more fully exlainedhereinafter.

The delay to which the signal is subjected in passing through the shiftregister 90 is inversely proportional to the shift rate and directlyproportional to the number of stages. The shift register delay is madeequal to the desired multipath delay At by controlling the shift rateand number of stages as follows:

Assume that the digital computer 26 has solved for the multipath delayA! corresponding to a particular set of variables at a particular timeand applies the reciprocal of this number to the D/A converter 120. Thesmaller the number At, the larger will be the DC. voltage output of theconverter 120. The voltage to frequency converter 124 provides afrequency determined by the voltage on line 122 and is used to shift theregister 90 and to control the signal sampling rate. By proper choice ofparameters this approach gives the de sired results.

Now, let m number of shift register 90 stages required to generate acertain delay At. Then m At times the shift rate. lfa delay of 0.0lseconds is desired and the shift rate is 15000 Hz, then m 0.0l 15000 I50stages. The shift rate is to be related to the rate at which the signalis sampled prior to AID conversion. The minimum sampling rate 3f, wheref, is the maximum signal frequency. Let the minimum shift rate E 3f, mn, where n is the number of bits used to define each sample.

Note that the sampling rate can be as much greater than the minimumvalue 3f, as desired.

Call the shift rate F,. Then,

m/At, a min mar n mlu and m f: max n mur Where Al is the maximum delayto be provided, and given F, m/At, then l mar rium/ Let the shift rateF, Va, where V is a DC voltage and a is a constant expressed in Hertzper volt. Then from the previous results,

Va m/At; or

V m/aAt.

shift rate/n 150,000/5 The last states that, for a given value of a andconstant dd product, the voltage V to be applied to the voltage tofrequency converter is directly proportional to the range r.

Keeping the above results in mind, further operation of FIG. 2 is asfollows:

The output frequency F of the voltage to frequency converter 124 is31",, mar n (Al /At) as discussed previously. A sample of F, is fed vialine 127 to divide by n divider 128, the multivibrator shaped output ofwhich is fed to the fixed delay 136. The output from the delay [36 isfed to one input of AND gates 80 94 and to the n-pulse generator 146.One component of the divide by n circuit 128 is also fed via line 148 asa read command to the A/D converter 74. When this occurs the converter74 changes the analog input amplitude to a n bit digital word in lessthan T seconds, the time delay of the fixed delay 136. At the end of T,seconds the delayed signal from 136 is applied to the AND gates 80 84transferring the contents of the AID converter to the shift register 90.The n pulse generator 146 is triggered by the trailing edge of thedelayed pulse from delay 136 to generate on line 154 a string of npulses which shift the register 90 n places. In the meantime, the A/Dconverter read signal has, by virtue ofline 150, enabled AND gates 96100 so as to read out the contents of the shift register 90 to the D/Aconverter 108. After n pulses, during which a different delayed wordsample is set up for readout and a new sample for read in, the abovesequence is repeated. Because of the use of the n -pulse generatortriggered by the trailing edge of the delayed signal from delay 136 togenerate shift pulses, instead of using the undivided output of thevoltage to frequency converter 124 to effect shifting, the A/Dconversion in converter 74, and the shift of the digital informationinto and out of the register can take n times as long.

The foregoing assumes that the computer output l/Al on line 28 isdigital. [f the computer 26 is analog in character and provides l/At interms of a voltage, then the D/A converter can be omitted and the computer output applied directly to the voltage to frequency converter 124.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. it is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed is:

1. Apparatus for generating electrical signals simula tive of active andpassive sonar signals arriving at a receiver via a plurality of paths,said apparatus compris a source 18) of active sonar simulatingelectrical sig nals;

a source (12) of passive sonar simulating electrical signals;

a first controllable delay network (22) connected to receive said activesignals and introduce a first delay;

a first phase shifter (38) connected to receive the output of said firstdelay network and introduce a first phase shift;

a first summing network (24) connected to combine said active signalswith the delayed and phase shifted output of said first phase shifter toprovide simulated target illuminating signals;

an echo synthesizer (44) connected to receive said target illuminatingsignals and operative to generate echo signals therefrom;

a second summing network (16) operative to combine said echo signalswith said passive signals;

a second controllable delay network (52) connected to receive the outputof said second summing network and operative to introduce a seconddelay;

a second phase shifter (62) connected to receive the output of saidsecond delay network and operative to introduce a second phase shift;

a third summing network 54 connected to receive and combine the outputsof said second summing network and said second phase shifter to producethe desired simulative multipath signals.

2. Apparatus as defined in claim 1, and further comprising:

a first variable attenuator means (32) connected to selectively vary theamplitude of delayed and phase shifted active signals; and

a second variable attenuator means (58) connected to selectively varythe amplitude of the delayed and phase shifted synthesizer and passivesource signals.

3. Apparatus as defined in claim 1, and comprising:

switch means (S1, S2, S3, S4) for selectively changing simulated pathcombinations.

4. Apparatus as defined in claim 1 and further comprising:

computer means (26) responsive to problem variables for providing delaycontrol signals; and

said first and second controllable delay network being responsive tosaid control signals to effect said first and second delays consistentwith said problem variables.

5. Apparatus as defined in claim 4 and wherein said first and secondcontrollable delay networks each comprise:

n bit analog to digital converter means (74) for converting said sonarsimulating signals from a characteristic frequency to n parallel digitalsignals;

an n channel, parallel-in, parallel-out shift register first gate means(80 84) connecting the output of said analog to digital converter meansto the input of said shift register;

an n bit digital to analog converter (108);

second gate means (96 100) connecting the output of said shift registerto the input of said digital to analog converter; and

control means responsive to said control signals and operative to enablesaid first and second gate means and to drive said shift register at ashift rate which will produce a delay consistent with said problemvariables.

6. Apparatus as defined in claim 5, and wherein said control meanscomprises:

a voltage to frequency converter (124) operative to provide a frequencyproportional to said delay control signals in response to an analogvoltage input;

a divide by n divider (128) connected to divide the output frequency ofsaid voltage to frequency converter to provide read signals to saidanalog to digital converter (74);

a first fixed delay means (136) connected between said output of saiddivider and said first gate means and providing delayed pulses so as toenable said first gate means after a first predetermined delay;

a n pulse generator connected to said first fixed delay means andtriggered by the trailing edge of each of the delayed pulses from saidfirst fixed delay means to generate as an output a string of n pulses,the output of said n pulse generator being connected to the shift inputof said shift register; and

said second gate means being enabled upon occurrence of said readsignals to read out said shift register to said digital to analogconverter U08)v 7. Apparatus as defined in claim 6, and:

said computer means (26) providing a digital output;

and

said control means comprising a digital to analog converter forproviding said analog voltage input to said voltage to frequencyconverter,

2. Apparatus as defined in claim 1, and further comprising: a firstvariable attenuator means (32) connected to selectively vary theamplitude of delayed and phase shifted active signals; and a secondvariable attenuator means (58) connected to selectively vary theamplitude of the delayed and phase shifted synthesizer and passivesource signals.
 3. Apparatus as defined in claim 1, and comprising:switch means (S1, S2, S3, S4) for selectively changing simulated pathcombinations.
 4. Apparatus as defined in claim 1 and further comprising:computer means (26) responsive to problem variables for providing delaycontrol signals; and said first and second controllable delay networkbeing responsive to said control signals to effect said first and seconddelays consistent with said problem variables.
 5. Apparatus as definedin claim 4 and wherein said first and second controllable delay networkseach comprise: n bit analog to digital converter means (74) forconverting said sonar simulating signals from a characteristic frequencyto n parallel digital signals; an n channel, parallel-in, parallel-outshift register (90); first gate means (80 - 84) connecting the output ofsaid analog to digital converter means to the input of said shiftregister; an n bit digital to analog converter (108); second gate means(96 - 100) connecting the output of said shift register to the input ofsaid digital to analog converter; and control means responsive to saidcontrol signals and operative to enable said first and second gate meansand to drive said shift register at a shift rate which will produce adelay consistent with said problem variables.
 6. Apparatus as defined inclaim 5, and wherein said control means comprises: a voltage tofrequency converter (124) operative to provide a frequency proportionalto said delay control signals in response to an analog voltage input; adivide by n divider (128) connected to divide the output frequency ofsaid voltage to frequency converter to provide read signals to saidanalog to digital converter (74); a first fixed delay means (136)connected between said output of said divider and said first gate meansand providing delayed pulses so as to enable said first gate means aftera first predetermined delay; a n pulse generator connected to said firstfixed delay means and triggered by the trailing edge of each of thedelayed pulses from said first fixed delay means to generate as anoutput a string of n pulses, the output of said n pulse generator beingconnected to the shift input of said shift register; and said secondgate means being enabled upon occurrence of said read signals to readout said shift register to said digital to analog converter (108). 7.Apparatus as defined in claim 6, and: said computer means (26) providinga digital output; and said control means comprising a digital to analogconverter (120) for providing said analog voltage input to said voltageto frequency converter.